This invention relates in general to management of power consumption by an integrated circuit, and in specific to a system and method that utilize on-chip voltage comparators to monitor the long-term (sustained) and short-term (instantaneous) power consumption of the chip to generate signals utilized for dynamically controlling operation of the chip in order to effectively manage its long-term and short-term power consumption.
Integrated circuits (commonly referred to as xe2x80x9cchipsxe2x80x9d), such as microprocessors, are utilized in an ever-increasing number of various applications. For instance, such chips are commonly implemented not only in personal computers (PCs) and laptops, but are typically implemented in much smaller (and more portable) devices, such as personal digital assistants (PDAs), cellular telephones, pagers, and various other types of devices. Considering the number of tasks that such chips are relied upon to perform, the desire for fast processing speeds (to allow tasks to be performed quickly), and the desire for limited power consumption by such chips, chip designers are faced with the difficult task of designing chips that achieve the desired performance (e.g., fast processing speed), while managing the power consumption of the chips. Given the ever-increasing advances being made in performance of chips, such as microprocessors, power consumption is becoming a serious concern. For example, power consumption is becoming a serious performance limiter for high speed microprocessors. For instance, it seems that with each succeeding generation of microprocessors, on-chip voltage-supply budgets dwindle while ac current consumption increases. Thus, a key design objective for microprocessor systems is providing the highest possible peak performance for compute-intensive code, while reducing power consumption of the microprocessor system. Particularly when such microprocessor systems are to be implemented within portable electronic devices, reduction in power consumption (at least during low performance periods) is desirable to maximize the battery life of the device.
As is well known, power consumption of a chip may be generally computed utilizing the following equation: P=C*V2*F, wherein P represents power consumption, C represents switching capacitance, V represents operating voltage, and F represents the clock frequency of the chip. In view of such equation, it should be understood that switching capacitance (C), voltage (V), and frequency (F) are all factors in determining the power consumption (P) of a chip. In many cases, it is necessary to limit processor frequency (F) and/or voltage (V) in order to hold the power consumption (P) of a chip below a certain level that is acceptable for use in a given system (e.g., within a desktop or portable devices).
Generally, two related power consumption concerns are present in chip designs. A first concern is the long-term (or sustainable) power consumption of the chip. In this regard, xe2x80x9clong-termxe2x80x9d (or sustainable) power consumption encompasses micro to millisecond time frame, which may be relatively long-term in operation of some chip designs. It is generally desirable to provide a chip design that provides a relatively low sustained power consumption. As described further below, prior art chip designers typically determine the maximum power that the chip may consume during worst case operation (e.g., during very compute-intensive operation), and may establish such determined maximum power as the sustained power to be supplied to the chip in order to allow for proper operation during worst case operations.
A second concern that arises with chip design is short-term (or instantaneous) power consumption. In this regard, xe2x80x9cshort-termxe2x80x9d (or instantaneous) power consumption encompasses nanosecond time frame. For example, a chip may, on average, require 20 watts of power, but may suddenly pull 100 watts of power. As those of ordinary skill in the art will appreciate, such a sudden step in power (e.g., a sudden step in the current load) will generally result in a droop in voltage. For instance, suppose that for all circuits on a chip to operate at a desired frequency (e.g., 1 gigahertz) the chip must receive a supply voltage above a particular minimum value, say 1 volt. Thus, in this example, if the voltage droops to 0.9 volt, then the circuits fail to operate at 1 gigahertz and the part will fail. Thus, it is necessary to ensure that the voltage does not droop below 1 volt in this example. If big step loads are encountered on the chip, then a guard band of additional voltage (above the required 1 volt) may need to be supplied to the chip. For instance, if step loads are encountered by the chip that result in a voltage droop up to 100 millivolts (i.e., 0.1 volt) at any instant, then 1.1 volts actually needs to be fed to the chip so that when a voltage droop of 0.1 volt is encountered the chip will still be supplied the necessary 1 volt to maintain proper operation at the 1 gigahertz frequency. That is, when a step load event is encountered, the voltage may droop briefly to 1 volt, and will then return to 1.1 volts. Thus, the additional 0.1 volt is required solely to guard band against step load events.
It is generally desirable to reduce the amount of sustained power required by a chip. Furthermore, it is generally desirable to reduce the amount of voltage droop that a chip encounters during operation (e.g., upon incurring step load conditions). Typically, such desires in designing chips are somewhat in conflict. For example, as a chip designer lowers the sustained power consumption of a chip, the chip generally encounters greater voltage droops (as a result of step loads). For instance, suppose a chip is designed having a sustainable power consumption of 60 watts, and from time to time briefly encounters step load conditions requiring 80 watts, thereby resulting in a voltage droop. Further suppose that the chip designer implements a design that reduces the chip""s sustainable power consumption to only 20 watts. If the chip continues to encounter such step load conditions requiring 80 watts, much greater voltage droops will be recognized. Thus, while the designer has reduced the long-term, sustainable power consumption of the chip, the voltage droop encountered by the chip is much greater. Accordingly, it is often difficult to effectively manage both the long-term, sustained power consumption, as well as the short-term power consumption of a chip.
Various prior art solutions have been implemented for managing long-term (sustainable) power consumption on a chip. Microprocessor chips of the prior art have typically been implemented with a fixed voltage and frequency determined to prevent the chip from consuming more than a particular amount of power. Typically, in designing prior art microprocessor chips, a designer tests the chip with software code for creating a heavy computational load on the chip in order to determine the appropriate voltage and frequency that may be implemented for the chip such that its power consumption does not exceed a particular amount when heavy computational loads are encountered by the chip. However, once implemented, such heavy computational loads may be encountered relatively seldom, with low (or no) computational load being placed on the microprocessor much of the time. Accordingly, the worst case computational loads dictate the voltage and frequency of the chip, thereby hindering performance of the chip (e.g., because of the decreased frequency required for the worst case) and resulting in inefficient use of power (as much of the power is wasted during most of the chip""s operation).
Prior art solutions have also been proposed for reducing the amount of voltage droops encountered on a chip (i.e., for managing a chip""s short-term power consumption). One power-saving technique implemented in prior art microprocessor chips involves regulating the voltage of the on-chip power supply to reduce voltage droops, thereby allowing for higher clock frequency to be implemented on the chip. More specifically, this technique attempts to improve the integrity of the on-chip power supply by regulating it carefully so that the average voltage to the chip can be reduced (i.e., because sudden changes in power consumption tend to cause the voltage to droop below average). For instance, a filtered version of the chip""s voltage may be monitored to detect whether it is above or below the chip""s average voltage at any given time. Power supplies commonly perform this kind of voltage regulation in attempt to maintain their output voltage constant. By reducing the droops through voltage regulation, the average voltage on the chip can be reduced by the magnitude of such droop reduction with no frequency reduction, and such reduction in average voltage results in reduced power consumption by the chip. Such an implementation that improves the integrity of the on-chip power supply to reduce voltage droops of a microprocessor is described in greater detail in An On-chip Voltage Regulator using Switched Decoupling Capacitors, by Michael Ang, Raoul Salem, and Alexander Taylor, published in ISSCC 2000 (White Paper 26.7), the disclosure of which is hereby incorporated herein by reference.
Such prior art technique generally aids in improving power integrity. However, such technique for improving power integrity attempts to supply extra current to a chip during high activity periods, thereby failing to actually reduce power consumption. Further, the additional current supplied during such periods is necessarily limited in supply by the quantity of capacitance. That is, this technique performs the function of reducing the overall variability of the power supply at the chip, thereby increasing the minimum voltage seen by the chip for a given average. This improves the power consumption at a particular operating frequency by reducing the average voltage (recall: P=CV2F). The amount of change in current that can be compensated by this technique is limited by the amount of charge that can be stored in the regulator""s capacitors, which in turn limits the benefit in terms of reduction in voltage droop.
In view of the prior art, a desire exists for a method and system for better managing power consumption of a chip. More particularly, a desire exists for a method and system for effectively managing long-term, sustained power consumption of a chip, while also managing short-term power consumption (e.g., to reduce voltage droops encountered).
The present invention is directed to a system and method which utilize analog detection of power consumption of an integrated circuit to enable management of such power consumption. Typical prior art power management techniques utilize digital detection of power consumption through such methods as utilizing circuitry and/or software to detect particular instruction sequences to be executed by the integrated circuit that are known to result in a large amount of power consumption. However, such digital detection methods often do not allow for accurate/precise detection of power consumption, and such digital detection methods are often not versatile in that instructions may be encountered for which the amount of power consumption that results from such instructions is unknown. Additionally, unanticipated conditions that result in large power consumption may be encountered during operation of the integrated circuit which such digital detection methods may be unable to detect. Various embodiments of the present invention utilize analog detection of power consumption. For instance, various embodiments of the present invention utilize on-chip circuitry to detect analog electrical characteristics of the chip, such as the voltage level on the chip, from which the chip""s power consumption may be determined. Such analog detection of power consumption enables a very accurate/precise management of a chip""s power consumption.
One embodiment of the present invention utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip. Such long-term, sustained power consumption is intended to encompass power consumption for approximately a microsecond, as well as more extended time frames. On-chip circuitry may be implemented to determined whether the chip""s power consumption is above a determined amount. For example, a predetermined average may be defined during development/testing of the chip, and circuitry may be implemented on the chip to detect when the chip""s power consumption is above such predetermined average. More specifically, a low-pass filter may be implemented on the chip to provide a low-pass filtered voltage for the chip. For instance, a resistor and capacitor may be arranged to form a low-pass filter, or any other suitable low-pass filter may be implemented on the chip to provide such low-pass filtered voltage. Additionally, a voltage comparator (e.g., an analog to digital converter) may be implemented on the chip. The voltage comparator receives as one input the low-pass filtered voltage of the chip. For its other input, the voltage comparator receives xe2x80x9cclean feedxe2x80x9d voltage that comprises voltage supplied to the chip by an off-chip power supply offset by a predetermined amount (such predetermined amount may, for example, correspond to the nominal DC voltage drop across the chip""s package parasitic resistance when its power consumption is equal to the predetermined average). If the voltage comparator determines that the low-pass filtered voltage is greater than the clean feed voltage, then the chip""s power consumption is known to be less than the predetermined average, and vice-versa.
The voltage comparator outputs a signal indicating whether the low-pass filtered voltage is greater than the clean feed voltage, and such signal may be input to on-chip control circuitry, which may manage the chip""s power consumption responsive to such signal. For instance, if determined that the chip""s long-term power consumption is too high (based on the output signal of the voltage comparator), the control circuitry may trigger certain operations to reduce the chip""s long-term power consumption. As one example of a power-reducing operation that may be triggered, certain functional units that are relatively big power consumers on the chip may be throttled.
Another embodiment of the present invention utilizes on-chip circuitry to manage short-term power consumption of the chip. Such short-term power consumption is intended to encompass power consumption for less than a microsecond (e.g., nanosecond time frame). On-chip circuitry may be implemented to determined whether the chip""s short-term power consumption is above a determined amount (which may be predetermined for the chip). More specifically, as described with the above embodiment, a low-pass filter may be implemented on the chip to provide a low-pass filtered voltage for the chip. Additionally, a voltage comparator (e.g., an analog to digital converter) may be implemented on the chip. The voltage comparator receives as one input the low-pass filtered voltage of the chip. For its other input, the voltage comparator receives the instantaneous on-chip voltage (i.e., the voltage present on the chip""s power grid). If the voltage comparator determines that the chip""s instantaneous voltage is greater than the low-pass filtered voltage, then the chip has entered a higher power consumption mode.
The voltage comparator outputs a signal indicating whether the chip""s instantaneous voltage is greater than the low-pass filtered voltage, and such signal may be input to on-chip control circuitry, which may manage the chip""s short-term power consumption responsive to such signal. For instance, if determined that the chip""s short-term power consumption is too high (based on the output signal of the voltage comparator), the control circuitry may trigger certain operations to quickly reduce the chip""s short-term power consumption. As one example of a power-reducing operation that may be triggered, certain functional units that are relatively big power consumers on the chip may be throttled.
A preferred embodiment of the present invention implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption. In this manner, analog detection of electrical characteristics (e.g., voltage) of an integrated circuit may be utilized to detect and manage both long-term and short-term power consumption of the chip.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.